View TMC2490AR2C_1326965.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

www.fairchildsemi.com
TMC2490A
Multistandard Digital Video Encoder
Features
* All-digital video encoding * Internal digital subcarrier synthesizer * 8-bit parallel CCIR-601/CCIR-656/ANSI/SMPTE 125M input format * CCIR-624/SMPTE-170M compliant output * Switchable chrominance bandwidth * Switchable pedestal with gain compensation * Pre-programmed horizontal and vertical timing * 13.5 Mpps pixel rate * Master or slave (CCIR656) operation * MPEG interface * Internal interpolation filters simplify output reconstruction filters * 10-bit D/A converters for video reconstruction * Supports NTSC and PAL standards * Closed-caption waveform insertion * Simultaneous S-Video (Y/C) output * Controlled edge rates * Single +5V power supply * 44 lead PLCC package * Parallel and serial control interface
Applications
* Set-top digital cable television receivers * Set-top digital satellite television receivers * Studio parallel CCIR-601 to analog conversion
Description
The TMC2490A video encoder converts digital component video (in 8-bit parallel CCIR-601/656 or ANSI/SMPTE 125M format) into a standard analog baseband television (NTSC, NTSC-EIA, and all PAL standards) signal with a modulated color subcarrier. Both composite (single lead) and S-Video (separate chroma and luma) formats are active simultaneously at all three analog outputs. Each video output generates a standard video signal capable of driving a singlyor doubly-terminated 75 Ohm load. The TMC2490A is intended for all non-Macrovision encoder applications. The TMC2490A is fabricated in a submicron CMOS process and is packaged in a 44-lead PLCC. Performance is guaranteed over the full 0C to 70C operating temperature range.
Block Diagram
LPF B-Y PD7-0 PIXEL DATA DEMUX AND SYNC EXTRACT PXCK Y HSYNC VSYNC, B/T SELC PDC/CBSEL DIGITAL SYNC AND BLANK GENERATOR INTERPOLATION FILTER REF SERIAL/PARALLEL CONTROL GLOBAL CONTROL VREF CBYP RREF
65-2490(1)A-01
INTERPOLATOR 4:2:2 TO 4:4:4 R-Y LPF
CHROMA MODULATOR INTERPOLATION FILTER
10-BIT D/A
CHROMA S-VIDEO LUMA COMPOSITE
SUBCARRIER SYNTHESIZER
10-BIT D/A
10-BIT D/A
SERIAL PARALLEL
SA1
SA0 ADR
SDA R/W
SCL CS
D7-0 D7-0
SER
RESET
REV. 1.0.2 2/27/02
TMC2490A
PRODUCT SPECIFICATION
Functional Description
The TMC2490A is a fully-integrated digital video encoder with simultaneous composite and Y/C (S-Video) outputs, compatible with NTSC, NTSC-EIA, and all PAL television standards. Digital component video is accepted at the PD port in 8-bit parallel CCIR-601/656 format. It is demultiplexed into luminance and chrominance components. The chrominance components modulate a digitally synthesized subcarrier. The luminance and chrominance signals are then separately interpolated to twice the input pixel rate and converted to analog signals by 10-bit D/A converters. They are also digitally combined and the resulting composite signal is output by a third 10-bit D/A converter. The TMC2490A operates from a single clock at 27 MHz, twice the system pixel rate. Programmable control registers allow software control of subcarrier frequency and phase parameters. Incoming YCBCR422 digital video is interpolated to YCBCR444 format for encoding. Internal control registers can be accessed over a standard 8-bit parallel microprocessor port or a 2-pin (clock and data) serial port.
Chroma Modulator
A digital subcarrier synthesizer generates the reference for a quadrature modulator, producing a digital chrominance signal. The chroma bandwidth may be programmed to 650 kHz or 1.3 MHz.
Interpolation Filters
Interpolation filters on the luminance and chrominance signals double the pixel rate to 27Mpps before D/A conversion. This low-pass filtering and oversampling process reduces sin(x)/x roll-off, and greatly simplifies the analog reconstruction filter required after the D/A converters.
D/A Converters
Analog outputs of the TMC2490A are driven by three 10-bit D/A converters, The outputs drive standard video levels into 37.5 or 75 Ohm loads. An internal voltage reference is used to provide reference current for the D/A converters. An external fixed or variable voltage reference source can also be used. The video signal levels from the TMC2490A may be adjusted to overcome the insertion loss of analog low-pass output filters by varying RREF or VREF.
Parallel and Serial Microprocessor Interfaces
The parallel microprocessor interface employs 11 pins. These are shared with the serial interface. A single pin, SER, selects between the two interface modes. In parallel interface mode, one address pin is decoded to enable access to the internal control register and its pointer. Controls are reached by loading a desired address through the 8-bit D7-0 port, followed by the desired data (read or write) for that address. The control register address pointer auto-increments to address 22h and then remains there. A 2-line serial interface is also provided on the TMC2490A for initialization and control. The same set of registers accessed by the parallel port is available to the serial port. The RESET pin sets all internal state machines and control registers to their initialized conditions, disables the analog outputs, and places the encoder in a reset mode. At the rising edge of RESET, the encoder is automatically initialized in NTSC-M format.
Sync Generator
The TMC2490A operates in master or slave mode. In slave mode, it extracts its horizontal and vertical sync timing and field information from the CCIR-656 SAV (Start of Active Video) and EAV (End of Active Video) signal in the incoming data stream. In master mode, it generates a 13.5 MHz timebase and sends line and field synchronizing signals to the host system. Horizontal and vertical synchronization pulses in the analog output are digitally generated by the TMC2490A with controlled rise and fall times on all sync edges, the beginning and end of active video, and the burst envelope. MSB PD7 PD7 PD7 PD7 CB (n) Y (n) CR (n) Y (n+1)
Figure 1. Pixel Data Format
LSB PD0 PD0 PD0 PD0
2
REV. 1.0.2 2/27/02
PRODUCT SPECIFICATION
TMC2490A
Pin Assignments
SDA/R/W SA0/ADR SA1 PD0 GND VDD PD1 PD2 PD3 PD4 PD5
6 5 4 3 2 1 44 43 42 41 18 19 20 21 22 23 24 25 26 27
HSYNC VSYNC,T/B CBSEL,PDC SELC RESET VDD GND PXCK VDD VREF RREF
28
SCL/CS SER D7 D6 D5 D4 GND D3 D2 D1 D0
40
7 8 9 10 11 12 13 14 15 16 17
39 38 37 36 35 34 33 32 31 30 29
TMC2490A
PD6 PD7 VDD GND CHROMA VDDA CBYP LUMA GND COMPOSITE GND
65-2490(1)A-02
Pin Descriptions
Pin Name Clock PXCK 25 TTL Pixel Clock Input. This 27.0 MHz clock is internally divided by 2 to generate the internal pixel clock. PXCK drives the entire TMC2490A, except the asynchronous microprocessor interface. All internal registers are strobed on the rising edge of PXCK. Pixel Data Inputs. Video data enters the TMC2490A on PD7-0 (Figure 1). Data I/O, General Purpose I/O, Chroma Input Port. When SER is HIGH, all control parameters are loaded into and read back over this 8-bit port. When SER = LOW, D0 can serve as a composite sync output, D1 outputs a burst flag during the back porch, D2-5 are General Purpose Outputs, and D6-7 are General Purpose Inputs. Master Reset Input. Bringing RESET LOW forces the internal state machines to their starting states and disables all outputs. Serial/Parallel Port Select. When SER is LOW, SA1 in conjunction with SA0 selects one of four addresses for the TMC2490A. Serial/Parallel Port Select. When SER is LOW, SA0 in conjunction with SA1 selects one-of-four addresses for the TMC2490A. When SER is HIGH, this control governs whether the parallel microprocessor interface selects a table address or reads/writes table contents. Pin Number Value Pin Function Description
Data Input Port PD7-0 38-44, 3 TTL
Microprocessor Interface D7-0 9-12, 14-17 TTL
RESET SA1
22 4
TTL TTL
SA0, ADR
5
TTL
3
TMC2490A
PRODUCT SPECIFICATION
Pin Descriptions (continued)
Pin Name SDA, R/W Pin Number 6 Value R-Bus/TTL Pin Function Description Serial Data/Read/Write Control. When SER is LOW, SDA is the data line of the serial interface. When SER is HIGH, the pin is the read/write control for the parallel interface. When R/W and CS are LOW, the microprocessor can write to the control registers over D7-0. When R/W is HIGH and CS is LOW, it can read the contents of any selected control register over D7-0. Serial Clock/Chip Select. When SER is LOW, SCL is the clock line of the serial interface. When SER is HIGH, the pin is the chip select control for the parallel interface. When CS is HIGH, the microprocessor interface port, D7-0, is set to HIGH impedance and ignored. When CS is LOW, the microprocessor can read or write parameters over D7-0. Serial/Parallel Port Select. When LOW, the 2-line serial interface is activated. Pins 5, 6, and 7 function as SA0, SDA, and SCL respectively. When HIGH, the parallel interface port is active and pins 5, 6, and 7 function as ADR, R/W, and CS respectively. Chrominance-only Video. Analog output of chrominance D/A converter. Maximum output is 1.35 volts peak-to-peak into a doubly terminated 75 Ohm load. Composite NTSC/PAL Video. Analog output of composite D/A converter. Maximum output is 1.35 volts peak-to-peak into a doubly terminated 75 Ohm load. Luminance-only Video. Analog output of luminance D/A converter. Maximum output is 1.35 volts peak-to-peak into a doubly terminated 75 Ohm load. Reference Bypass Capacitor. Connection point for 0.1 F decoupling capacitor to VDD at pin 34. Current-setting Resistor. Connection point for external currentsetting resistor for D/A converters. The resistor is connected between RREF and GND. Output video levels are inversely proportional to the value of RREF. Voltage Reference Input. External voltage reference input, internal voltage reference output, nominally 1.235 V. Horizontal Sync Output. Vertical Sync Output or Odd/Even Field ID Output. Pixel Data Phase Output or Video Blanking Output. Luma/Chroma MUX Control. Power Supply. Positive power supply. Ground. Analog Power Supply. Positive power supply.
SCL, CS
7
R-Bus/TTL
SER
8
TTL
Outputs CHROMA 35 1.35V p-p
COMPOSITE
30
1.35V p-p
LUMA
32
1.35V p-p
Analog Interface CBYP RREF 33 28 0.1F 787
VREF SYNC Out HSYNC VSYNC, T/B CBSEL, PDC SELC Power Supply VDD GND VDDA
27
+1.235V
18 19 20 21 1, 23, 26, 37 2, 13, 24, 29, 31, 36 34
TTL TTL TTL TTL +5V 0.0V +5V
REV. 1.0.2 2/27/02
4
PRODUCT SPECIFICATION
TMC2490A
Control Registers
The TMC2490A is initialized and controlled by a set of registers which determine the operating modes. An external controller is employed to write and read the Control Registers through either the 8-bit parallel or 2-line serial interface port. The parallel port, D7-0, is governed by pins CS, R/W, and ADR. The serial port is controlled by SDA and SCL.
Table 1. Control Register Map
Reg 00 01 02 03 04 04 04 04 04 04 04 05 05 05 05 05 05 05 05 06 06 06 070D Bit 7-0 7-0 7-0 7-0 7 6 5 4 3 2 1-0 7 6 5 4 3 2 1 0 7-6 5-3 2-0 7-0 Mnemonic PARTID2 PARTID1 PARTID0 REVID MASTER NGSEL YCDELAY RAMPEN YCDIS COMPDIS FORMAT PALN BURSTF CHRBW SYNCDIS BURDIS LUMDIS CHRDIS PEDEN Reserved FIELD Reserved Reserved Function Reads back 97h Reads back 24h Reads back 90h (91h) Silicon revision # Master Mode NTSC Gain Select Luma to chroma delay Modulated ramp enable LUMA, CHROMA disable COMPOSITE disable Television standard select Select PAL-N Subcarrier Burst flag disable Chroma bandwidth select Sync pulse disable Color burst disable Luminance disable Chrominance disable Pedestal enable Program LOW Field ID (Read only) Program LOW Program LOW 20 21 22 22 22 22 22 101F 7-0 Reg 0E 0E 0E 0E 0F 0F 0F 0F 0F Bit 7 6 1 0 7 5 4 3 1-0 Mnemonic PORT7-6 PORT5-2 BURSTF CSYNC PED21 VSEL CBSEL VBIEN HDSEL Reserved Function General purpose Inputs General purpose Outputs Burst Flag Output Composite Sync Output VBI Pedestal Enable Vertical Sync Select CBSEL/PDC Pin Function VBI Pixel Data Enable HSYNC Delay May be left unprogrammed TMC2490A Identification Registers (Read only) General Purpose Port Register
Global Control Register
General Control Register
Reserved Registers
Video Output Control Register
Closed-Caption Insertion Registers 7-0 7-0 7 6 5 4 3-0 CCD1 CCD2 CCON CCRTS CCPAR CCFLD CCLINE First Byte of CC Data Second Byte of CC Data Enable CC Data Packet Request To Send Data Auto Parity Generation CC Field Select CC Line Select
Field ID Register
Notes: 1. For each register listed above, all bits not specified are reserved and should be set to logic LOW to ensure proper operation.
Reserved Registers
REV. 1.0.2 2/27/02
5
TMC2490A
PRODUCT SPECIFICATION
Table 2. Default Register Values on Reset
Reg 00 01 02 03 Dflt 97 24 90(91) xx Reg 04 05 06 07 Dflt 00 01 00 00 Reg 08 09 0A 0B Dflt 00 00 00 00 Reg 0C 0D 0E 0F Dflt 00 00 00 F2 Reg 20 21 22 Dflt 80 80 00
Control Register Definitions
Reg 00 01 02 03 Bit 7-0 7-0 7-0 7-0 Name PARTID2 PARTID1 PARTID0 REVID Description Reads back 97h Reads back 24h Reads back 90h (91h) Reads back a value corresponding to the revision letter of the silicon.
Global Control Register (04)
7 MASTER Reg 04 Bit 7 6 NGSEL Name MASTER 5 YCDELAY 4 RAMPEN 3 YCDIS 2 COMPDIS 1 FORMAT 0
Description Master Mode. When MASTER = 1, the encoder generates its own video timing and outputs signals VSYNC (or T/B), HSYNC, SELC, and PDC (or CBSEL). When MASTER = 0, the TMC2490A extracts timing from the embedded EAV codeword in the video datastream and optionally outputs signals VSYNC (or T/B), HSYNC, SELC, and PDC (or CBSEL). NTSC Gain Selection. Luma to chroma delay. When HIGH, the luminance path within the TMC2490A is delayed by one PXCK period. The delay applies to both COMPOSITE and LUMA outputs and may be used to compensate for group delay variation of external filters. When LOW, luminance and chrominance have the same latency. Modulated ramp enable. When HIGH, the TMC2490A outputs a modulated ramp test signal. When LOW, incoming digital video is encoded. LUMA, CHROMA disable. When HIGH, the LUMA and CHROMA outputs are disabled. Set LOW for normal enabled operation. COMPOSITE disable. When HIGH, the COMPOSITE output is disabled. Set LOW for normal enabled operation. Television standard select. Selects basic H&V timing parameters and subcarrier frequency. Pedestal level and chrominance bandwidth are independently programmed. 0 0 1 1 0 1 0 1 NTSC PAL-B,G,H,I,N PAL-M Reserved
04 04
6 5
NGSEL YCDELAY
04 04 04 04
4 3 2 1-0
RAMPEN YCDIS COMPDIS FORMAT
REV. 1.0.2 2/27/02
6
PRODUCT SPECIFICATION
TMC2490A
Control Register Definitions (continued)
Video Output Control Register (05)
7 PALN Reg 05 Bit 7 6 BURSTF Name PALN 5 CHRBW 4 SYNCDIS 3 BURDIS 2 LUMDIS 1 CHRDIS 0 PEDEN
Description Select PAL-N Subcarrier. When HIGH, selects PAL-N subcarrier frequency. When LOW, the encoder produces the PAL-B,G,H,I subcarrier. Program LOW for NTSC and PAL-M video. Burst flag disable. When BURSTF is LOW, a clamp gate signal is produced on the D1 output and register 0E bit 1. Chroma bandwidth select. When LOW, the chrominance bandwidth is 650 kHz. When HIGH, the chrominance bandwidth is 1.3 MHz. Sync pulse disable. When HIGH, horizontal and vertical sync pulses on the COMPOSITE video output are suppressed (to blanking level). Color burst, active video, and the CSYNC output remain active. Set LOW for normal composite video operation. Color burst disable. When HIGH, color burst is suppressed to the blanking level. Set LOW for normal operation. Luminance disable. When HIGH, incoming Y values are forced to black level. Color burst, CHROMA, and sync are not affected. Set LOW for normal operation. Chrominance disable. When HIGH, incoming color components CB and CR are suppressed, enabling monochrome operation. Output color burst is not affected. Set LOW for normal color operation. Pedestal enable. When LOW, black and blanking are the same level for ALL lines. When HIGH, a 7.5 IRE pedestal is inserted into the output video for NTSC and PAL-M lines 23-262 and 286-525 only. Chrominance and luminance gain factors are adjusted to keep video levels within range. PEDEN is valid for NTSC and PAL-M only and should be LOW for all other formats.
05 05 05
6 5 4
BURSTF CHRBW SYNCDIS
05 05
3 2
BURDIS LUMDIS
05
1
CHRDIS
05
0
PEDEN
Field Data Register (06)
7 Reserved Reg 06 06 06 Bit 7-6 5-3 2-0 Name Reserved FIELD Reserved 6 5 4 FIELD Description Program LOW. Field ID (Read only). A value of 000 corresponds to field 1 and 111 corresponds to field 8. Program LOW. 3 2 1 Reserved 0
7
TMC2490A
PRODUCT SPECIFICATION
Control Register Definitions (continued)
Reserved Registers (07-0D)
7 6 5 4 Reserved Reg 07- 0D Bit 7-0 Name Reserved Description Program LOW. 3 2 1 0
General Purpose Port Register (0E)
7 PORT7 Reg 0E 0E Bit 7-6 5-2 6 PORT6 Name PORT7-6 PORT5-2 5 PORT5 4 PORT4 3 PORT3 2 PORT2 1 BURSTF 0 CSYNC
Description General purpose Inputs. When in serial control mode, these register readonly bits indicate the state present on data port pins D7 and D6. General purpose Outputs. When in serial control mode or when reading register 0E in parallel control mode, these register read/write bits drive data pins D5-D2 to the state contained in the respective register bits. Burst Flag Output. Produces Burst Flag on data pin D1 when in serial control mode, or when reading register 0E. Composite Sync Output. Produces Composite Sync on data pin D0 when in serial control mode, or when reading register 0E.
0E 0E
1 0
BURSTF CSYNC
REV. 1.0.2 2/27/02
8
PRODUCT SPECIFICATION
TMC2490A
Control Register Definitions (continued)
General Control Register (0F)
7 PED21 Reg 0F Bit 7 6 Reserved Name PED21 5 VSEL 4 CBSEL 3 VBIEN 2 1 Reserved 0
Description VBI Pedestal Enable. When HIGH and FORMAT is 00 (NTSC) or 10 (PAL-M), pedestal is added to lines 21, 22, 283, 284, 285. When LOW, no pedestal is placed on these lines. PED21 is valid for NTSC and PAL-M only and should be LOW for all other formats. Program HIGH. Vertical Sync Select. When LOW, the TMC2490A outputs a traditional vertical sync on VSYNC. When HIGH, the chip outputs odd/even field identification on the VSYNC pin, with 0 denoting an odd field. CBSEL/PDC pin function. When CBSEL = 0, the PDC signal is produced on the CBSEL/PCD pin. When CBSEL = 1, the CBSEL signal is produced on the CBSEL/PDC pin. VBI Pixel Data Enable. When VBIEN = 0, the vertical interval lines are blanked. When VBIEN = 1, Pixel data is encoded into the VBI lines. Program LOW. Sync Delay. HDEL shifts the falling edge of the H and V syncs relative to the PD port. HDEL Result 00 H and V syncs are aligned with luminance pixel 735 (Y735) 01 H and V syncs are aligned with Blue color difference pixel 735 (Cb736) 10 H and V syncs are aligned with luminance pixel 736 (Y736) 11 H and V syncs are aligned with Red color difference pixel 735 (Cr736) Refer to Figure 2a, HDEL Timing
0F 0F
6 5
Reserved VSEL
0F
4
CBSEL
0F 0F 0F
3 2 1-0
VBIEN Reserved HDEL
Reserved Registers (10-1F)
7 6 5 4 Reserved Reg 10- 1F Bit 7-0 Name Reserved Description May be left unprogrammed 3 2 1 0
9
PRODUCT SPECIFICATION
TMC2490A
Control Register Definitions (continued)
Closed-Caption Insertion (20)
7 6 5 4 CCD1 Reg 20 Bit 7-0 Name CCD1 Description First Byte of CC Data. Bit 0 is the LSB. The MSB will be overwritten by an ODD Parity bit if CCPAR is HIGH. 3 2 1 0
Closed-Caption Insertion (21)
7 6 5 4 CCD2 Reg 21 Bit 7-0 Name CCD2 Description Second Byte of CC Data. Bit 0 is the LSB. The MSB will be overwritten by an ODD Parity bit if CCPAR is HIGH. 3 2 1 0
Closed-Caption Insertion (22)
7 CCON Reg 22 22 Bit 7 6 6 CCRTS Name CCON CCRTS 5 CCPAR 4 CCFLD 3 2 CCLINE 1 0
Description Enable CC Data Packet. Command the CC data generator to send either CC data or a NULL byte whenever the specified line is transmitted. Request To Send Data. This bit is set HIGH by the user when bytes 20 and 21 have been loaded with the next two bytes to be sent. When the encoder reaches the falling edge of the HSYNC preceding the line specified in bits 4-0 of this register, data will be transferred from registers 20 and 21, and RTS will be reset LOW. A new pair of bytes may then be loaded into registers 20 and 21. If CCON = 1 and CCRTS = 0 when the CC line is to be sent, NULL bytes will be sent. Auto Parity Generation. When set HIGH, the encoder replaces the MSB of bytes 20 and 21 with a calculated ODD parity. When set LOW, the CC processor transmits the 16 bits exactly as loaded into registers 20 and 21. CC Field Select. When LOW, CC data is transmitted on the selected line of ODD fields. When HIGH, it is sent on EVEN fields. CC Line Select. Defines (with an offset) the line on which CC data is transmitted.
22
5
CCPAR
22 22
4 3-0
CCFLD CCLINE
10
PRODUCT SPECIFICATION
TMC2490A
General Purpose Port
The TMC2490A provides a general purpose I/O port for system utility functions. Input, output, and sync functions are implemented. Register 0E is the General Purpose Register. Full functionality is provided when the encoder is in Serial control mode (SER = LOW). Most of the functions are available in parallel interface mode (SER = HIGH).
In serial control mode, these same data output pins (D1-0) always act as a burst flag and composite sync TTL outputs, the conditions of the serial control notwithstanding. The states of the flags may be read over the serial port, but due to the low frequency of the serial interface, it may be difficult to get meaningful information.
Pixel Interface
The TMC2490A interfaces with an 8-bit 13.5 Mpps (27 MHz) video datastream. It will automatically synchronize with embedded Timing Reference Signals, per CCIR-656. It also includes a master sync generator on-chip, which can produce timing reference outputs.
General Purpose Input (serial mode only)
Bits 7 and 6 of Register 0E are general purpose inputs. When the encoder is in serial control mode, data bits D7 and D6 are mirrored to these register locations. When Register 0E is read, the states of bits 7 and 6 reflect the TTL logic levels present on D7 and D6, respectively, at the time of read command execution. Writing to these bits has no effect. This function is not available when the encoder is in parallel control mode.
CCIR-656 Mode
When operating in CCIR-656 Mode (MASTER = 0), the TMC2490A identifies the SAV and EAV 4-byte codewords embedded in the video datastream to derive all timing. Both SAV and EAV are required.
General Purpose Output
Register 0E read/write bits 5-2 are connected to pins D5-2, respectively, when the encoder is in serial control mode. The output pins continually reflects the values most recently written into register 0E (1 = HIGH, 0 = LOW). Note that these pins are always driven outputs when the encoder is in serial control mode. When register 0E is read, these pins report the values previously stored in the corresponding register bits, i.e., it acts as a read/write register. When the encoder is in parallel control mode, this reading produces the output bit values on the corresponding data pins, just as in the serial control mode. However, the values are only present when reading register 0E. The controller can command a continuous read on this register to produce continuous outputs from these pins.
MASTER Mode
When in MASTER Mode (MASTER = 1), the Encoder produces its own timing, and provides HSYNC, VSYNC (or B/T), SELC, and PDC (or CBSEL) to the Pixel Data Source.
SELC Output
The SELC output toggles at 13.5 MHz (1/2 the pixel rate), providing a phase reference for the multiplexed luma/chroma CCIR-656 datastream. It is HIGH during the rising edge of the clock intended to load chroma data. This is useful when interfacing with a 16-bit data source, and can drive a Y/C multiplexer.
CBSEL Output
The CBSEL output identifies the CB element of the CB-YCR-Y CCIR-656 data sequence. It is HIGH during the rising edge of the clock to load CB data. This will prevent unintentionally swapping the CB and CR color components when operating in MASTER mode and reading data from a framestore.
Burst Flag and Composite Sync (output/ read-only)
Register 0E bit 1 is associated with the encoder burst flag. It is a 1 (HIGH) from just before the start of the color burst to just after the end of the burst. It is a 0 (LOW) at all other times. Register 0E bit 0 outputs the encoder composite sync status. It is a 0 (LOW) during horizontal and vertical sync tips. It is a 1 (HIGH) at all other times. These register bits may be read at any time over either the serial or parallel control port. Since they are dynamic, their states will change as appropriate during a parallel port read. In fact, if the parallel control port is commanded to read register 0E continually, the pins associated with these bits behave as burst flag and composite sync timing outputs.
PDC Output
The PDC output is a blanking signal, indicating when the encoder expected to receive pixel data. When PDC is HIGH, the incoming PD is encoded.
REV. 1.0.2 2/27/02
11
TMC2490A
PRODUCT SPECIFICATION
1464 1472 PXCK
1592 1600
1727 1715
0 0
625-line 525-line
PD7-0
CB732 Y732 CR732 Y733 CB734 Y734 CR734 Y735 CB736 Y736 CR736 CB800 Y800 CR800 Y801 CB801 CR856 Y857
CB0
Y0
CR0
Y1
CB2
CBSEL
HYSNC HDEL = 00 HDEL = 01 HDEL = 10 HDEL = 11
65-2490A-03
Figure 2a. HDEL TIming
1430 1435 PXCK
1440 1440
1464 1472
1724 1712
1727 1715
0 0
17 3
625-line 525-line
tSP PD7-0 FF 00 EAV HSYNC (Output) HDEL = 2 tDO PDC 00 FV1 tDO tHS FF 00 00 FV0 CB0
tHP Y0
SAV
tDO
65-2490A-04
Figure 2b. CCIR-656 Horizontal Interval Timing Detail
1430 1435 PXCK
1440 1440
1464 1472
1727 1715
0 0
17 3
625-line 525-line
tS PD7-0 tDO HSYNC (Output) HDEL = 2 tDO PDC tHS CB0
tH Y0
tDO
65-2490A-05
Figure 3. Master Mode Horizontal Interval Timing Detail
Horizontal and Vertical Timing
Horizontal and vertical video timing in the TMC2490A is preprogrammed for line-locked systems with a 2x pixel clock of 27.0 MHz. Table 3 and Table 4 show timing parameters for NTSC and PAL standards and the resulting TMC2490A analog output timing. The user provides exactly 720 pixels of active video per line. In master mode, the TMC2490A precisely controls the duration and activity of every segment of the horizontal line and vertical field group. In external sync slave mode, it holds the end-of-line blank state (e.g. front porch for active video lines) until it receives the next horizontal sync signal.
In CCIR-656 slave mode, it likewise holds each end-of-line blank state until it receives the next end of active video (EAV) signal embedded in the incoming data stream. The vertical field group comprises several different line types based upon the Horizontal line time. H = (2 x SL) + (2 x SH) [Vertical sync pulses] = (2 x EL) + (2 x EH) [Equalization pulses]
SMPTE 170M NTSC and Report 624 PAL video standards call for specific rise and fall times on critical portions of the video waveform. The chip does this automatically, requiring no user intervention. The TMC2490A digitally defines
12
REV. 1.0.2 2/27/02
PRODUCT SPECIFICATION
TMC2490A
slopes compatible with SMPTE 170M NTSC or CCIR Report 624 PAL on all vital edges: 1. 2. Sync leading and trailing edges. Burst envelope.
3. 4.
Active video leading and trailing edges. All vertical interval equalization pulse and sync edges.
Table 3. Horizontal Timing Standards and Actual Values for 60 fps Video Standards (s)
NTSC (SMPTE 170M) Parameter Front porch Horiz. Sync Breezeway Color Burst Color Back porch Blanking Active Video Line Time Equalization HIGH Equalization LOW Sync HIGH Sync LOW Sync rise and fall times FP SY BR BU CBP BL VA H EH EL SH SL 10.5 52.56 2.235 Min 1.4 4.6 Nom 1.5 4.7 0.608 2.514 1.378 10.7 52.86 63.556 29.5 2.3 4.7 27.1 14020ns 11.0 53.06 2.794 Max 1.6 4.8 PAL-M (CCIR 624) Min 1.27 4.6 0.9 2.237 0.503 10.7 52.46 10.9 52.66 63.556 29.5 2.3 4.7 27.1 <250 ns 4.7 1.1 2.517 Nom Max 2.22 4.8 1.3 2.797 2.363 11.1 52.86 TMC2490A 1.53 4.74 0.59 (NTSC) 1.04 (PAL-M) 2.31 1.65 (NTSC) 0.89 (PAL-M) 10.8 52.633 63.557 29.47 2.31 4.67 27.13 135ns
Table 4. Horizontal Timing Standards and Actual Values for 50 fps Video Standards (s)
PAL-B,G,H,I (CCIR 624) Parameter Front porch Horiz. Sync Breezeway Color Burst Color Back porch Blanking Active Video Line Time Equalization HIGH Equalization LOW Sync HIGH Sync LOW Sync rise and fall times FP SY BR BU CBP BL VA H EH EL SH SL 11.7 51.7 Min 1.2 4.5 0.6 2.030 Nom 1.5 4.7 0.9 2.255 2.654 12.0 52.0 64 29.65 2.35 4.7 27.3 25050 ns 12.3 52.3 11.7 51.7 Max 1.8 4.9 1.2 2.481 Min 1.2 4.5 0.6 2.233 PAL-N (CCIR 624) Nom 1.5 4.7 0.9 2.513 2.387 12.0 52.0 64 29.65 2.35 4.7 27.3 200100 ns 12.3 52.3 Max 1.8 4.9 1.2 2.792 TMC2490A 1.57 4.74 0.89 2.3 2.3 1.8 52.2 64.0 29.63 2.37 4.67 27.3 250
13
TMC2490A
PRODUCT SPECIFICATION
H H/2 BURST CBP EH VA FP SY BR BU VA
24318B
SL SH
24319A
EL
Figure 4. Horizontal Blanking Interval Timing
Figure 5. Vertical Sync and Equalization Pulse Detail
524
525
FIELDS 1 AND 3
10
...
19
20
21
22
UVV COMPOSITE SYNC HSYNC VSYNC
UVV
EE
EE
EE
SS
SS
SS
EE
EE
EB
UBB
UBB
UBB
UVV
UVV
B/T 262 263 FIELDS 2 AND 4 264 265 266 267 268 269 270 271 272 273 ... 282 283 284 285
UVV COMPOSITE SYNC HSYNC VSYNC
UVE
EE
EE
ES
SS
SS
SE
EE
EE
EB
UBB
UBB
UVV
UVV
UVV
B/T
24492B
Figure 6. NTSC Vertical Interval
14
REV. 1.0.2 2/27/02
PRODUCT SPECIFICATION
TMC2490A
Table 6. NTSC Field/Line Sequence and Identification
Field 1, FID = 00 Line 1 2 3 4 5 6 7 8 9 10 ... 20 21 ... 262 263 ID EE EE EE SS SS SS EE EE EE UBB ... UBB UVV ... UVV UVE Field 2, FID = 01 Line 264 265 266 267 268 269 270 271 272 273 ... 282 283 ... 524 525 ID EE EE ES SS SS SE EE EE EB UBB ... UBB UVV ... UVV UVV Field 3, FID = 10 Line 1 2 3 4 5 6 7 8 9 10 ... 20 10 ... 262 263
EB UBB UVV UVE
Field 4, FID = 11 Line 264 265 266 267 268 269 270 271 272 273 ... 282 273 ... 524 525 ID EE EE ES SS SS SE EE EE EB UBB ... UBB UVV ... UVV UVV
ID EE EE EE SS SS SS EE EE EE UBB ... UBB UVV ... UVV UVE
EE Equalization pulse SE Half-line vertical sync pulse, half-line equalization pulse SS Vertical sync pulse ES Half-line equalization pulse, half-line vertical sync pulse
Equalization broad pulse Black and Burst1 Active video Half-line video, half-line equalization pulse
Note: 1. VBB lines are changed to UVV (Active Video) when VBIEN = 1.
15
TMC2490A
PRODUCT SPECIFICATION
1247
1248
FIELDS 1 AND 5
6
7
...
22
23
24
25
26
1249
1
2
3
4
5
UVV COMPOSITE SYNC HSYNC VSYNC B/T 309
-VE
EE
EE
SS
SS
SE
EE
EE
-BB
UBB
...
UBB
UVV
UVV
UVV
UVV
310
FIELDS 2 AND 6
319
320
...
334
335
336
337
311
312
313
314
315
316
317
318
UVV COMPOSITE SYNC HSYNC VSYNC B/T 622
-VV
EE
EE
ES
SS
SS
EE
EE
EB
UBB
UBB
...
UBB
UBB
UVV
UVV
623
FIELDS 3 AND 7
631
632
...
647
648
649
650
651
624
625
626
627
628
629
630
-VV COMPOSITE SYNC HSYNC VSYNC B/T 934
-VE
EE
EE
SS
SS
SE
EE
EE
UBB
UBB
...
UBB
UVV
UVV
UVV
UVV
935
FIELDS 4 AND 8
944
945
...
959
960
961
962
936
937
938
939
940
941
942
943
UVV COMPOSITE SYNC HSYNC VSYNC B/T
UVV
EE
EE
ES
SS
SS
EE
EE
EB
-BB
UBB
...
UBB
UBB
UVV
UVV
24495B
Figure 7. PAL-B,G,H,I,N Vertical Interval
REV. 1.0.2 2/27/02
16
PRODUCT SPECIFICATION
TMC2490A
Table 7. PAL-B,G,H,I,N Field/Line Sequence and Identification
Fields 1 and 5 FID = 000, 100 Line 1 2 3 4 5 6 7 8 ... 22 23 ... 308 309 310 311 312 ID SS SS SE EE EE -BB UBB UBB ... UBB UVV ... UVV UVV -VV EE EE Fields 2 and 6 FID = 001, 101 Line 313 314 315 316 317 318 319 320 ... 335 336 ... 621 622 623 624 625 ID ES SS SS EE EE EV UBB UBB ... UBB UVV ... UVV -VV -VE EE EE Fields 3 and 7 FID = 010, 110 Line 626 627 628 629 630 631 632 633 ... 647 648 ... 933 934 935 936 937
UBB UVV -BB -VV -VE
Fields 4 and 8 FID = 011, 111 Line 938 939 940 941 942 943 944 945 ... 960 961 ... 1246 1247 1248 1249 1250 ID ES SS SS EE EE EB -BB UBB ... UBB UVV ... UVV UVV -VE EE EE
ID SS SS SE EE EE UBB UBB UBB ... UBB UVV ... UVV UVV UVV EE EE
Burst1
EE Equalization pulse SE Half-line vertical sync pulse, half-line equalization pulse SS Vertical sync pulse ES Half-line equalization pulse, half-line vertical sync pulse EB Equalization broad pulse
Black and Active video Blank line with color burst suppression 2 Active video with color burst suppressed Half-line video, half-line equalization pulse, color burst suppressed
Notes: 1. VBB lines are changed to UVV (Active Video) when VBIEN = 1. 2. -BB lines are changed to -VV (Active Video, Burst Suppressed) when VBIEN = 1.
17
TMC2490A
PRODUCT SPECIFICATION
521
522
FIELDS 1 AND 5
7
8
9
...
17
18
523
524
525
1
2
3
4
5
6
UVV COMPOSITE SYNC HSYNC VSYNC B/T 259
UVV
EE
EE
EE
SS
SS
SS
EE
EE
EE
-BB
-BB
UBB
...
UBB
UVV
260
FIELDS 2 AND 6
270
271
...
279
280
281
261
262
263
264
265
266
267
268
269
UVV COMPOSITE SYNC HSYNC VSYNC B/T 521
-VE
EE
EE
ES
SS
SS
SE
EE
EE
EB
-BB
UBB
...
UBB
UVV
UVV
522
FIELDS 3 AND 7
7
8
9
...
17
18
523
524
525
1
2
3
4
5
6
UVV COMPOSITE SYNC HSYNC VSYNC B/T 258 259
-VV
EE
EE
EE
SS
SS
SS
EE
EE
EE
-BB
-BB
UBB
...
UBB
UVV
260
FIELDS 4 AND 8
270
271
...
279
280
281
261
262
263
264
265
266
267
268
269
UVV COMPOSITE SYNC HSYNC VSYNC B/T
-VV
-VE
EE
EE
ES
SS
SS
SE
EE
EE
EB
-BB
UBB
...
UBB
UVV
UVV
24496B
Figure 8. PAL-M Vertical Interval
REV. 1.0.2 2/27/02
18
PRODUCT SPECIFICATION
TMC2490A
Table 8. PAL-M Field/Line Sequence and Identification
Field 1 and 5 FID = 000, 100 Line 1 2 3 4 5 6 7 8 9 ... 17 18 ... 258 259 260 261 262 ID SS SS SS EE EE EE -BB -BB UBB ... UBB UVV ... UVV UVV -VE EE EE Field 2 and 6 FID = 001, 101 Line 263 264 265 266 267 268 269 270 271 ... 279 280 ... 521 522 523 524 525 ID ES SS SS SE EE EE EB -BB UBB ... UBB UVV ... UVV -VV EE EE EE Field 3 and 7 FID = 010, 110 Line 1 2 3 4 5 6 7 8 9 ... 17 18 ... 258 259 260 261 262
UBB UVV -BB -VV UVV
Field 4 and 8 FID = 011, 111 Line 263 264 265 266 267 268 269 270 271 ... 279 280 ... 521 522 523 524 525 ID ES SS SS SE EE EE EB -BB UBB ... UBB UVV ... UVV UVV EE EE EE
ID SS SS SS EE EE EE -BB UBB UBB ... UBB UVV ... UVV -VV -VE EE EE
EE Equalization pulse SE Half-line vertical sync pulse, half-line equalization pulse SS Vertical sync pulse ES Half-line equalization pulse, half-line vertical sync pulse EB Equalization broad pulse -VEHalf-line video, half-line equalization pulse, color burst suppressed
Black and Burst1 Active video Blank line with color burst suppression 2 Active video with color burst suppressed Half-line black, half-line video
Notes: 1. VBB lines are changed to UVV (Active Video) when VBIEN = 1 2. -BB lines are changed to -VV (Active Video, Burst Suppressed) when VBIEN = 1
Subcarrier Generation and Synchronization
The color subcarrier is generated by an internal digital frequency synthesizer. The subcarrier synthesizer gets its frequency and phase values preprogrammed into the TMC2490A. In Master Mode, the subcarrier is internally synchronized on field 1 of the eight-field sequence to establish and maintain a specific relationship between the leading edge of horizontal sync and color burst phase (SCH). Proper subcarrier phase is maintained through the entire eight field set, including the 25 Hz offset in PAL-N/B/I systems. The subcarrier is reset to the phase values found in Table 9.
SCH Phase Control
SCH refers to the timing relationship between the 50% point of the leading edge of horizontal sync and the first positive or negative zero-crossing of the color burst subcarrier reference. In PAL, SCH is defined for line 1 of field 1, but since there is no color burst on line 1, SCH is usually measured at line 7 of field 1. The need to specify SCH relative to a particular line in PAL is due to the 25 Hz offset of PAL subcarrier frequency. Since NTSC has no such 25 Hz offset, SCH applies to all lines.
REV. 1.0.2 2/27/02
19
TMC2490A
PRODUCT SPECIFICATION
Table 9. Subcarrier and Color Burst Reset Values
NTSC Digital field: Line number: Subcarrier phase reset value: Resultant color burst phase: 1 4 180 PAL-M 1 4 0 PALB,G,H,I,N 1 1 0
Luminance Processing
During horizontal and vertical blanking, the luma processor generates blanking levels and properly timed and shaped sync and equalization pulses. During active video, it captures and rescales the incoming Y components and adds the results to the blank level to complete a proper monochrome television waveform, which is then upsampled to drive the luma D/A and the composite adder. For NTSC-EIA (5:2 white:sync, no black pedestal), the overall luma input-to-output equation for 00
+135
+135
Note: 1. Line numbering is in accordance with Figure 6, Figure 7, and Figure 8. Subcarrier and color burst phase are relative to the horizontal reference of the line specified above.
Table 10. Standard Subcarrier Parameters
Standard NTSC PAL B,G,H,I PAL-M PAL-N Horizontal Subcarrier Frequency (KHz) Frequency (MHz) 15.734266 15.625000 15.734266 15.625000 3.579545455 4.43361875 3.57561189 3.58205625
Table 11. Luminance Input Codes
PD7-0 Input Dec 255 254 235 16 1 0 Hex FF FE EB 10 01 00 Reserved 100% white Black Luma Level (CCIR-601) Reserved NTSC, PAL-M Luma Level (IRE) PEDEN = 0 0 108.7 100 0 -6.9 0 PEDEN = 1 7.5 108 100 7.5 1.2 7.5 PAL-B,G,H,I,N Luma Level (mV) 0 761 700 0 -48 0
Table 12. D/A Converter and Analog Levels
NTSC, PAL-M Video Level Maximum Output 100% white Black Blank Sync White-to-blank White-to- sync Color burst p-p D/A 1022 820 284 240 12 580 808 232 IRE 134.8 100 7.5 0 -40 100 140 40 NTSC w/o Setup D/A 1022 820 240 240 12 580 808 232 IRE 138.4 100 0 0 -40 100 140 40 PAL-B,G,H,I,N D/A 1022 800 240 240 0 560 800 244 mV 817 700 0 0 -300 700 1000 300
20
REV. 1.0.2 2/27/02
PRODUCT SPECIFICATION
TMC2490A
Filtering Within the TMC2490A
The TMC2490A incorporates internal digital filters to establish appropriate bandwidths and simplify external analog reconstruction filter designs. The chroma portion of the incoming digital video is bandlimited to reduce edge effect and other distortions of the image compression process. Chrominance bandwidth is selected by CHRBW. When LOW, the chrominance passband attenuation is <3 dB within 650 kHz from fSC. The stopband rejection is >26 dB outside fSC 2 MHz. When HIGH, the chrominance passband attenuation is <3 dB within 1.3 MHz from fSC. The stopband rejection is >33 dB outside fSC 4 MHz.
0 -10 Attenuation (dB) -20 -30 -40 -50 -60 -70 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 24490A Frequency (MHz) Narrowband Wideband
Virtually all digital-to-analog converters have a response with high frequency roll-off as a result of the zero-order hold characteristic of classic D/A converters. This response is commonly referred to as a sin(x)/x response. The sin(x)/x vs. sampling frequency is shown in Figure 12.
0.5 0.0 Attenuation (dB) -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 -3.5 0 1 2 3 4 Frequency (MHz) 5 6
24488A
Figure 11. Chrominance and Luminance Interpolation Filter - Passband Detail
Figure 9. Color-Difference Low-Pass Filter Response
The Chroma Modulator output and the luminance data are digitally filtered with sharp-cutoff low-pass interpolation filters. These filters ensure that aliased subcarrier, chrominance, and luminance frequencies are sufficiently suppressed above the video base-band.
0 -10 Attenuation (dB) -20 -30 -40 -50 -60 -70 0 1 2 3 4 56789 Frequency (MHz) 10 11 12 13
24487A
The TMC2490A's digital interpolation filters convert the data stream to a sample rate of twice the pixel rate. This results in much less high frequency sin(x)/x rolloff and the output spectrum between fS/4 and 3 x fS/4 contains very little energy. Since there is so little signal energy in this frequency band, the demands placed on the output reconstruction filter are greatly reduced. The output filter needs to be flat to fS/4 and have good rejection at 3 x fS/4. The relaxed requirements greatly simplify the design of a filter with good phase response and low group delay distortion. A small amount of peaking may be added to compensate residual sin(x)/x rolloff.
0 -1
Attenuation (dB)
-2 -3
Fs=27.0Msps (Oversampled)
Fs=13.5Msps -4 -5 -6 0 1 2 3 4 5 Frequency (MHz) 6 7 8
24489A
Figure 10. Chrominance and Luminance Interpolation Filter - Full Spectrum Response
Figure 12. Sin(x)/x Response
REV. 1.0.2 2/27/02
21
TMC2490A
PRODUCT SPECIFICATION
Closed Caption Insertion
The TMC2490A includes a flexible closed caption processor. It may be programmed to insert a closed caption signal on any line within a range of 16 lines on ODD and/or EVEN fields. Closed Caption insertion overrides all other configurations of the encoder. If it is specified on an active video line, it takes precedence over the video data and removes NTSC setup if setup has been programmed for the active video lines. 3. Write into register 22 the proper combination of CCFLD and CCLINE. CCPAR may be written as desired. Set CCRTS HIGH. The CC data is transmitted during the specified line.
4.
As soon as CCDx is transferred into the CC processor (and CCRTS goes LOW), new data may be loaded into registers 20 and 21. This allows the user to transmit CC data on several consecutive lines by loading data for line n+1 while data is being sent on line n. Registers 20-21 auto-increment when read or written. Register 22 does not. The microcontroller can repeatedly read register 22 until CCRTS is found to be LOW, then address register 20 and write three auto-incremented bytes to set up for the next CC line.
Closed Caption Control
Closed caption is turned on by setting CCON HIGH. Whenever the encoder begins producing a line specified by CCFLD and CCLINE, it will insert a closed caption line in its place. If CCRTS is HIGH, the data contained in CCDx will be sent. IF CCRTS is LOW, Null Bytes (hex 00 with ODD parity) will be sent.
Parallel Microprocessor Interface
The parallel microprocessor interface, active when SER is HIGH, employs an 11-line interface, with an 8-bit data bus and one address bit: two addresses are required for device programming and pointer-register management. Address bit 0 selects between reading/writing the register addresses and reading/writing register data. When writing, the address is presented along with a LOW on the R/W pin during the falling edge of CS. Eight bits of data are presented on D7-0 during the subsequent rising edge of CS. In read mode, the address is accompanied by a HIGH on the R/W pin during a falling edge of CS. The data output pins go to a low-impedance state tDOZ ns after CS falls. Valid data is present on D7-0 tDOM after the falling edge of CS.
Line Selection
The line to contain CC data is selected by a combination of the CCFLD bit and the CCLINE bits. CCLINE is added to the offset shown in Table 13 to specify the line.
Table 13. Closed Caption Line Selection
Standard 525 625 Offset 12 274 9 321 Field ODD EVEN ODD EVEN Lines 12-27 274-289 9-24 321-336
Parity Generation
Standard Closed-Caption signals employ ODD parity, which may be automatically generated by setting CCPAR HIGH. Alternatively, parity may be generated externally as part of the bytes to be transmitted, and, with CCPAR LOW, the entire 16 bits loaded into the CCDx registers will be sent unchanged.
Table 14. Parallel Port Control
ADR 1 1 0 0 R/W 0 1 0 1 Action Load D7-0 into Control Register pointer. Read Control Register pointer on D7-0. Write D7-0 to addressed Control Register. Read addressed Control Register on D7-0.
Operating Sequence
A typical operational sequence for closed-caption insertion on Line 21 is: 1. 2. Read Register 22 and check that bit 6 is LOW, indicating that the CCDx registers are ready to accept data. If ready, write two bytes of CC data into registers 20 and 21.
22
REV. 1.0.2 2/27/02
PRODUCT SPECIFICATION
TMC2490A
tPWLCS SCL/CS tSA SDA / R/W tHA
tPWHCS
SA0/ADR tSD D7-0
65-3548-02
tHD
Figure 13. Microprocessor Parallel Port - Write Timing
tPWLCS SCL/CS tSA SDA / R/W tHA
tPWHCS
SA0/ADR tDOM D7-0 tDOZ
65-3548-03
tHOM
Figure 14. Microprocessor Parallel Port - Read Timing
Serial Control Port (R-Bus)
In addition to the 11-wire parallel port, a 2-wire serial control interface is also provided, and active when SER is LOW. Either port alone can control the entire chip. Up to four TMC2490A devices may be connected to the 2-wire serial interface with each device having a unique address. The 2-wire interface comprises a clock (SCL/CS) and a bidirectional data (SDA/R/W) pin. The TMC2490A acts as a slave for receiving and transmitting data over the serial interface. When the serial interface is not active, the logic levels on SCL/CS and SDA/R/W are pulled HIGH by external pullup resistors. Data received or transmitted on the SDA/R/W line must be stable for the duration of the positive-going SCL/CS pulse. Data on SDA/R/W can only change when SCL/CS is LOW. If SDA/R/W changes state while SCL/CS is HIGH, the serial interface interprets that action as a start or stop sequence. There are five components to serial bus operation: * Start signal * Slave address byte
* Base register address byte * Data byte to read or write * Stop signal When the serial interface is inactive (SCL/CS and SDA/R/W are HIGH) communications are initiated by sending a start signal. The start signal is a HIGH-to-LOW transition on SDA/R/W while SCL/CS is HIGH. This signal alerts all slaved devices that a data transfer sequence is coming. The first eight bits of data transferred after a start signal comprise a seven bit slave address and a single R/W bit. As shown in Figure 16A, the R/W bit indicates the direction of data transfer, read from or write to the slave device. If the transmitted slave address matches the address of the device (set by the state of the SA0/ADR and SA1 input pins in Table 15), the TMC2490A acknowledges by bringing SDA/R/W LOW on the 9th SCL/CS pulse. If the addresses do not match, the TMC2490A does not acknowledge.
REV. 1.0.2 2/27/02
23
TMC2490A
PRODUCT SPECIFICATION
Table 15. Serial Port Addresses
A6 0 0 0 0 A5 0 0 0 0 A4 0 0 0 0 A3 1 1 1 1 A2 1 1 1 1 A1 A0 (SA1) (SA0) 0 0 1 1 0 1 0 1
are available addresses, the address will not increment and will remain at its maximum value of 22h. Any base address higher than 22h will not produce an ACKnowledge signal. Data is read from the control registers of the TMC2490A in a similar manner. Reading requires two data transfer operations: * The base address must be written with the R/W bit of the slave address byte LOW to set up a sequential read operation. * Reading (the R/W bit of the slave address byte HIGH) begins at the previously established base address. The address of the read register auto-increments after each byte is transferred. To terminate a read/write sequence to the TMC2490A, a stop signal must be sent. A stop signal comprises of a LOW-toHIGH transition of SDA/R/W while SCL/CS is HIGH. A repeated start signal occurs when the master device driving the serial interface generates a start signal without first generating a stop signal to terminate the current communication. This is used to change the mode of communication (read, write) between the slave and master without releasing the serial interface lines.
Data Transfer via Serial Interface
For each byte of data read or written, the MSB is the first bit of the sequence. If the TMC2490A does not acknowledge the master device during a write sequence, the SDA/R/W remains HIGH so the master can generate a stop signal. If the master device does not acknowledge the TMC2490A during a read sequence, the TMC2490A interprets this as "end of data." The SDA/R/ W remains HIGH so the master can generate a stop signal. Writing data to specific control registers of the TMC2490A requires that the 8-bit address of the control register of interest be written after the slave address has been established. This control register address is the base address for subsequent write operations. The base address auto-increments by one for each byte of data written after the data byte intended for the base address. If more bytes are transferred than there
SDA / R/W tBUFF tSTAH tDAL SCL/CS tDAH
24469A
tDHO
tDSU
tSTASU
tSTOSU
Figure 15. Serial Port Read/Write Timing
24
REV. 1.0.2 2/27/02
PRODUCT SPECIFICATION
TMC2490A
Serial Interface Read/Write Examples
Write to one control register * * * * * Start signal Slave Address byte (R/W bit = LOW) Base Address byte Data byte to base address Stop signal
Read from one control register * * * * * * * * Start signal Slave Address byte (R/W bit = LOW) Base Address byte Stop signal Start signal Slave Address byte (R/W bit = HIGH) Data byte from base address No Acknowledge
Write to four consecutive control registers * * * * * * * * Start signal Slave Address byte (R/W bit = LOW) Base Address byte Data byte to base address Data byte to (base address + 1) Data byte to (base address + 2) Data byte to (base address + 3) Stop signal
Read from four consecutive control registers * * * * * * * * * * * Start signal Slave Address byte (R/W bit = LOW) Base Address byte Stop signal Start signal Slave Address byte (R/W bit = HIGH) Data byte from base address Data byte from (base address + 1) Data byte from (base address + 2) Data byte from (base address + 3) No Acknowledge
SDA / R/W
MSB
LSB
ACK
SCL/CS
24470A
Figure 16. Serial Interface - Typical Byte Transfer
SDA / R/W
A6
A5
A4
A3
A2
SA1
SA0
R/W
ACK
SCL/CS
65-3548-05
Figure 16A. Chip Address with Read/Write Bit
REV. 1.0.2 2/27/02
25
TMC2490A
PRODUCT SPECIFICATION
Equivalent Circuits and Threshold Levels
VDD VDD
p RREF VREF
p n VDD p
OUT GND
27012B
GND
27013B
Figure 18. Equivalent Analog Input Circuit
Figure 19. Equivalent Analog Output Circuit
VDD
VDD
p Digital Input n
p Digital Output n
GND
27014C
GND
27011C
Figure 20. Equivalent Digital Input Circuit
Figure 21. Equivalent Digital Output Circuit
tENA
CS Three-State Outputs
tDIS
0.5V 2.0V 0.8V
7048C
High Impedance
0.5V
Figure 22. Threshold Levels for Three-State Measurements
REV. 1.0.2 2/27/02
26
PRODUCT SPECIFICATION
TMC2490A
Absolute Maximum Ratings
(beyond which the device may be damaged)1 Parameter Power Supply Voltage Digital Inputs Applied Voltage2 Forced Current3,4 Output Applied Voltage2 Forced Current3,4 Short Circuit Duration (single output in HIGH state to ground) Analog Short Circuit Duration (all outputs to ground) Temperature Operating, Ambient Junction Storage Temperature Lead Soldering (10 seconds) Vapor Phase Soldering (1 minute) -65 -20 110 140 150 300 220 C C C C C Infinite -0.5 -3.0 VDD + 0.5 6.0 1 V mA sec -0.5 -20.0 VDD + 0.5 20.0 V mA Min. -0.5 Typ. Max. 7.0 Unit V
Notes: 1. Functional operation under any of these conditions is NOT implied. Performance and reliability are guaranteed only if Operating Conditions are not exceeded. 2. Applied voltage must be current limited to specified range. 3. Forcing voltage must be limited to specified range. 4. Current is specified as conventional current flowing into the device.
Operating Conditions
Parameter VDD VIH Power Supply Voltage Input Voltage, Logic HIGH TTL Compatible Inputs CLK Input R-Bus Inputs VIL VREF IREF RREF IOH IOL TA Input Voltage, Logic LOW External Reference Voltage D/A Converter Reference Current External Reference Resistor Output Current, Logic HIGH Output Current, Logic LOW Ambient Temperature, Still Air 0 (IREF = VREF/RREF), flowing out of the RREF pin VREF = NOM, RL = 75 TTL Compatible Inputs R-Bus Inputs 1.235 1.57 787 -2.0 4.0 70 Conditions Min. 4.75 2.0 2.4 0.7VDD GND 0.8 0.3VDD V mA mA mA C V Typ. 5.0 Max. 5.25 VDD VDD Units V V
27
TMC2490A
PRODUCT SPECIFICATION
Operating Conditions (continued)
Parameter Pixel Interface fPXL fPXCK tPWHPX tPWLPX tSP tHP tPWLCS tPWHCS tSA tHA tSD tHD tPWLR tDAL tDAH tSTAH tSTASU tSTOSU tBUFF tDSU tDHO Pixel Rate Master Clock Rate PXCK pulse width, HIGH PXCK pulse width, LOW PD7-0 Setup Time PD7-0 Hold Time CS Pulse Width, LOW CS Pulse Width, HIGH Address Setup Time Address Hold Time Data Setup Time (write) Data Hold Time (write) RESET Pulse Width, LOW SCL Pulse Width, LOW SCL Pulse Width, HIGH SDA Start Hold Time SCL to SDA Setup Time (Stop) SCL to SDA Setup Time (Start) SDA Stop Hold Time Setup SDA to SCL Data Setup Time SDA to SCL Data Hold Time = 2X pixel rate 10 15 15 0 95 3 17 0 17 0 16 1.3 0.6 0.6 0.6 0.6 1.3 300 300 13.5 27.0 Mpps MHz ns ns ns ns ns pixels ns ns ns ns PXCK s s s s s s ns ns Conditions Min. Typ. Max. Units
Parallel Microprocessor Interface
Serial Microprocessor Interface
REV. 1.0.2 2/27/02
28
PRODUCT SPECIFICATION
TMC2490A
DC Electrical Characteristics
Parameter IDD IDDQ VRO IBR ZRO IIH IIL IOZH IOZL IOS VOH VOL CI CI VOC ROUT COUT Power Supply Current, Unloaded Voltage Reference Output Reference Bias VREF Output Impedance Input Current, HIGH Input Current, LOW Hi-Z Output Leakage Current, Output HIGH Hi-Z Output Leakage Current, Output LOW Short-Circuit Current Output Voltage, HIGH Output Voltage, LOW Digital Input Capacitance Digital Output Capacitance Video Output Compliance Video Output Resistance Video Output Capacitance IOUT = 0mA, f = 1MHz -0.3 15 15 25 IOH = Max IOL = Max 4 10 2.0 VDD = Max, VIN = VDD VDD = Max, VIN = 0V VDD = Max, VIN = VDD VDD = Max, VIN = 0V -50 2.4 0.4 10
1
Conditions VDD = Max, fPXCK = 27MHz VDD = Max
Min.
Typ.
Max. 130 20
Units mA mA V A A A A A mA V V pF pF V k pF
Power Supply Current, Quiescent2
1.173 -100
1.235 1000
1.297 100 10 10 10 10 -10
Notes: 1. Maximum IDD with VDD = Max and TA = Min. Outputs loaded wtih 75. 2. IDDQ when RESET = LOW, disabling D/A converters.
AC Electrical Characteristics
Parameter tDOZ tHOM tDOM tR tF tDOV Output Delay, CS to low-Z Output Hold Time, CS to high-Z Output Delay, CS to Data Valid D/A Output Current Risetime D/A Output Current Falltime Analog Output Delay 10% to 90% of full scale 90% to 10% of full scale 3 Conditions Min. 14 30 40 2 2 11 17 Typ. Max. Units ns ns ns ns ns ns
Note: 1. Timing reference points are at the 50% level. Analog CLOAD <10pF, D7-0 load <40pF.
29
TMC2490A
PRODUCT SPECIFICATION
System Performance Characteristics
Parameter RES dp dg CNLP CNLG CLIM CLGI CLDI LNLD FTWD LTWD NOISE CAMN CPMN SYR SYF PSRR D/A Converter Resolution Differential Phase Differential Gain Chroma Nonlinear Phase Chroma Nonlinear Gain Chroma/Luma Intermodulation Chroma/Luma Gain inequality Chroma/Luma Delay inequality Luma Nonlinear Distortion Field Time Waveform Distortion Line Time Waveform Distortion Noise Level 1 Chroma AM Noise Chroma PM Noise Sync Pulse Rise Time Sync Pulse Fall Time Power Supply Rejection Ratio PXCK = 27 MHz, 40 IRE Ramp PXCK = 27 MHz, 40 IRE Ramp NTC-7 Combination NTC-7 Combination NTC-7 Combination NTC-7 Composite NTC-7 Composite NTC-7 NTC-7 NTC-7 100% unmod. ramp Red field Red field NTSC PAL NTSC PAL CBYP = 0.1 F, f = 1 kHz Conditions Min. 10 Typ. 10 0.6 0.7 0.3 TBD 0.3 TBD 7.1 TBD 0.1 0.3 -55 -63 -62 140 250 140 250 0.02 %/%VDD ns Max. 10 Units Bits degree % degree % IRE % ns % % % dB rms dB rms dB rms ns
Note: 1. Noise Level is uniformly weighted, 10 kHz to 5.0 MHz bandwidth, with Tilt Null ON measured using VM700 "Measure Mode."
REV. 1.0.2 2/27/02
30
PRODUCT SPECIFICATION
TMC2490A
Applications Information
The circuit in Figure 24 shows the connection of power supply voltages, output reconstruction filters and the external voltage reference. All VDD pins should be connected to the same power source. The full-scale output voltage level, VOUT, on the COMPOSITE, LUMA, and CHROMA pins is found from: VOUT where: = IOUT x RL = K x IREF x RL = K x (VREF/RREF) x RL
The reference voltage in Figure 24 is from an LM185 1.2 Volt band-gap reference. The 392 Ohm resistor connected from RREF to ground sets the overall "gain" of the three D/A converters of the TMC2490A. A 787 resistor is used for single 75 termination. Varying RREF 5% will cause the full-scale output voltage on COMPOSITE, LUMA, and CHROMA to vary by 5%. The suggested output reconstruction filter is the same one used on the TMC2063P7C Demonstration Board. The phase and frequency response of this filter is shown in Figure 23. The Schottky diode is for ESD protection.
Analog Reconstruction Filter
* IOUT is the full-scale output current sourced by the TMC2490A D/A converters. * RL is the net resistive load on the COMPOSITE, CHROMA, and LUMA output pins. * K is a constant for the TMC2490A D/A converters (approximately equal to 10.4). * IREF is the reference current flowing out of the RREF pin to ground. * VREF is the voltage measured on the VREF pin. * RREF is the total resistance connected between the RREF pin and ground. * A 0.1F capacitor should be connected between the CBYP pin and the adjacent VDDA, pin.
40 0 0 -10
Attenuation (dB)
-20 -30 -40 -50 -60 0 5 10 15 Frequency (MHz) 20 -80 -120 -160 -200 25
24365A
Figure 23. Response of Recommended Output Filter
VIDEO FROM ENCODER
1.8H 75 27pF 75 +5V 100pF 330pF 330pF 1N5818
VIDEO OUTPUT TO 75 LOAD
+5V 10F 27.0 MHz CLOCK VIDEO INTERFACE PIXCLK B/T HSYNC YC7-0 PXCK VSYNC HSYNC PD7-0 VDD 0.1F
1.0H
GND
LPF CHROMA LUMA COMPOSITE VDDA CBYP 0.1F D7-0 SCL/CS SDA / R/W 3.3k VREF 392 RREF LM185-1.2 0.1F
TMC2490A
Multistandard Digital Video Encoder
+5V
MPEG-2 Decoder
SELC
SER RESET SA1 SA0/ADR
PDC
CONTROL INTERFACE
65-2490(1)A-03
Figure 24. Typical Application Circuit
REV. 1.0.2 2/27/02
31
Phase (deg)
-40
TMC2490A
PRODUCT SPECIFICATION
Notes:
32
REV. 1.0.2 2/27/02
PRODUCT SPECIFICATION
TMC2490A
Notes:
REV. 1.0.2 2/27/02
33
TMC2490A
PRODUCT SPECIFICATION
Notes:
34
REV. 1.0.2 2/27/02
PRODUCT SPECIFICATION
TMC2490A
Mechanical Dimensions - 44-Pin PLCC Package
Symbol A A1 A2 B B1 D/E D1/E1 D3/E3 e J ND/NE N ccc Inches Min. Max. Millimeters Min. Max. Notes: Notes 1. All dimensions and tolerances conform to ANSI Y14.5M-1982 2. Corner and edge chamfer (J) = 45 3. Dimension D1 and E1 do not include mold protrusion. Allowable protrusion is .101" (.25mm)
.165 .180 .090 .120 .020 -- .013 .021 .026 .032 .685 .695 .650 .656 .500 BSC .050 BSC .042 .056 11 44 -- .004
4.20 4.57 2.29 3.04 .51 -- .33 .53 .66 .81 17.40 17.65 16.51 16.66 12.7 BSC 1.27 BSC 1.07 1.42 11 44 -- 0.10
3
2
E E1 J
D
D1
D3/E3 B1 e J
A A1 A2 B -C- LEAD COPLANARITY
ccc C
35
TMC2490A
PRODUCT SPECIFICATION
Ordering Information
Product Number TMC2490AR2C Temperature Range 0C to 70C Screening Commercial Package 44-Lead PLCC Package Marking 2490AR2C
DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.
www.fairchildsemi.com 2/27/02 0.0m 003 Stock# DS7002490A 1998 Fairchild Semiconductor Corporation
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

▲Up To Search▲

Price & Availability of TMC2490AR2C

	To Download TMC2490AR2C Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .